1. Field of the Invention
The present invention relates to a processing system including a computer system having a testing mechanism (for example, a JTAG circuit as a boundary scan architecture) for testing a high-density printed circuit board, particularly to a technique for reading out data from a memory such as a ROM by using the testing mechanism.
2. Description of the Related Art
High-density integration in chip parts including LSIs has eagerly been sought in recent years and more complicated circuits can be mounted on a smaller chip. The surface mounting technique on a printed circuit board has also advanced so that more chips can be mounted on the printed circuit board. Owing to the advancement of these fields, a higher-performance system can be built up in a smaller size; on the other hand, it has become difficult to test chip parts on such a printed circuit board.
Accordingly, to test such a high-density printed circuit board, JTAG (Joint Test Action Group) has proposed aboard testing technique (test simplifying technique) as a standard of IEEE standard 1149.1. In this board testing technique, a boundary scan architecture (hereafter, referred to as JTAG circuit) is defined as a testing mechanism incorporated into chip parts including LSIs.
In this JTAG circuit (also mentioned as JTAG scan circuit), shift-type scan chains are provided with input and output pins of chip parts mounted on a printed circuit board and the scan chains for the chip parts are connected on the printed circuit board. Thereby, the state of the input and output pins can be controlled and observed only by the scan shift operation without directly probing the input and output pins of the chip parts on the printed circuit board.
A general circuit construction of the JTAG circuit will be described with reference to FIG. 6. The circuit is comprised of five tap access ports (hereafter referred to as TAP for abbreviation) 501.about.505 as described later, a TAP controller 51, a data register group 52, an instruction register (IR) 53, a data register selector 54 output selecting circuit 55 and a gate circuit 56.
The TAP 501 is an input terminal to receive a test clock signal TCK, and the TAP 502 is an input terminal to receive a test mode selecting signal TMS. The TAP 503 is an input terminal to receive data necessary for testing, this TAP 503 is hereafter noted as a test data input TDI. The TAP 504 is an output terminal to supply a test result of an LSI (chip) provided with the JTAG circuit, this TAP 504 is hereafter noted as a test data output TDO. Furthermore, the TAP 505 is to receive a test reset signal TRST to initialize test logic in the JATG circuit.
The TAP controller 51 controls, by means of the test mode selecting signal TMS and the test clock signal TCK, the shift operation whereby the input data from the test data input TDI is sent to the instruction register 53 or to the data register group 52. Furthermore, this TAP controller 51 controls the register selecting operation by the output selecting circuit 55 and the gate operation by the gate circuit 56.
The data register group 52 consists of a user test data register 520, boundary scan register 521, and bypass register 522.
The user test data register 520 stores an arbitrary test data that a user individually determines, and is composed of shift registers. The boundary scan register 521 is composed of one stage shift registers provided in correspondence with terminals of the part (here, an LSI) to be tested, and captures or holds signals appearing on the terminals of the LSI on the basis of the theory of the scan test The bypass register 522 is composed of one stage shift registers, and it enables the input data from the test data input TDI to bypass the circuit between the test data input TDI and the output selecting circuit 55 so that the input data can go through the circuit as it is from the test data output TDO. Therefore, this bypass register 522 is used when bypassing data from this JTAG circuit to the other JTAG circuit on the subsequent stage.
On the other hand, the instruction register 53 writes a command (register designating command) from the test data input TDI by the shift operation.
The data register selector 54 analyzes the command written in the instruction register 53, and selects the register specified by the command out of the data register group 52. The data are written into the register selected by this data register selector 54 by the shift operation When either the boundary scan register 521 or user test data register 520 is selected, the data are written; when the bypass register 522 is selected, the bypassing operation mentioned above is done by the bypass register 522.
The output selecting circuit 55 is composed of a multiplexer (MUX) 551 and 552.
The multiplexer 551 is controlled by the TAP controller 51 to select one of the registers 520.about.522 of the data register group 52, and sends out data of the selected register.
The multiplexer 552 is controlled by the TAP controller 51 to select either the data from the data register group 52 (the output from the multiplexer 551) or the data from the instruction register 53, and sends out the selected data.
The gate circuit 56 is controlled by the TAP controller 51 to open or close, and when the gate circuit 56 opens, sends out the data from output selecting circuit 55 (the data from the multiplexer 552) to the test data output TDO.
The JTAG circuit thus constructed is usually applied to the test of a printed circuit board containing chip parts into which the JTAG circuit is integrated. However in recent years, it has been done to set data during a test or normal operation in a circuit such as a register in a system logic circuit (data loading), or to read out data from a circuit such as a register in a system logic circuit (data sensing). The access command issued to a system logic circuit by using the JTAG circuit is called the JTAG command.
In the JTAG circuit performing a data loading or data sensing by the JTAG command, as shown in FIG. 7, a JTAG instruction register (hereafter, abbreviated as JIR) 523 and a JTAG data register (hereafter, abbreviated as JDR) 524 are provided in replacement of the user test data register 520 shown in FIG. 6.
The JIR 523 functions as a storage of the command for controlling the system logic circuit in this LSI and consists of shift registers (or, shift registers and latch circuits), and sequentially shifts and receives the input data from the test data input TDI. When a specific command is set in this JIR 523, the command in the JIR 523 is transferred into a command analyzing unit in the command control unit (not illustrated), and the command is analyzed therein.
The JDR 524 functions as a storage of the data to be written into the system logic circuit in this LSI and the data read out from the system logic circuit in this LSI, and consists of shift registers (or, shift registers and latch circuits) in the same manner as the JIR 523.
When the data are written into this JDR 524, the input data from the test data input TDI are sequentially shifted and received. When specific data are set, the data in the JDR 524 are transferred to a processing unit in the foregoing command controlling unit, and a process is executed on the basis of an analyzed result by the foregoing command analyzing unit. It is possible, for example, to set data in the register of the system logic circuit performing a normal operation, to set a specific value to a counter, or to reset only a specific circuit in this LSI.
On the contrary, it is possible to read out the data of the system logic circuit performing a normal operation from the test data output TDO through the JDR 524. Namely, the data set in the register in the system logic circuit are transferred to the JDR 524, the data of the JDR 524 are sequentially shifted, and thereby, the shifted data are sent out from the test data output TDO.
The data-write into the JIR 523 or JDR 524 is done, as described above, with a shift operation when the data register selector 54 selects the JIR 523 or JDR 524.
Next, the operation of the JTAG circuit (executing operation of the JTAG command) comprising the JIR 523 and JDR 524 will be described with reference to FIG. 8. FIG. 8 is a flow chart showing a state transition of the test logic. The state transition of the test logic is controlled by the TAP controller 51 to embody various test states The TAP controller 51 is controlled by the test clock signal TCK, test mode selecting signal TMS, and test reset signal TRST entering from the TAP 501, 502, and 505, respectively
Immediately after initialized, the TAP controller 51 is in the TEST-LOGIC-RESET state (S201). In this state, the test logic is unavailable, and the normal operation of the system logic is 15 possible.
Each of the states is transferred in accordance with the state of the test mode selecting signal TMS when the test clock signal TCK rises When the state is in the TEST-LOGIC-RESET state (S201), for example, the test clock signal TCK rises, and if the test mode selecting signal TMS at that moment is "0", the state is transferred to the RUN-TEST/IDLE state (S202); if the test mode selecting signal TMS at that moment is "1", the state is held in the TEST-LOGIC-RESET state (S201).
The RUN-TEST/IDLE state (S202) is the basic state during a test being executed, which is a state that a scan operation is about to start, or an intermediate state during the scan operation
When the state is transferred to the SELECT-DR-SCAN state (S203), the scan sequence is initialized.
Next, the state is transferred into the CAPTURE-DR state (S211) or into the SELECT-IR-SCAN state (S204) in accordance with the state of the test mode selecting signal TMS. Here, the transition to the SELECT-IR-SCAN state (S204) to perform a scan operation to the instruction register 53 will be described. When the state is transferred to the SELECT-IR-SCAN state (S204), the scan sequence of the instruction register 53 is initialized.
When the state is transferred to the CAPTURE-IR state (S205), a fixed pattern is captured in the shift registers forming the instruction register 53. This fixed pattern has a fixed binary code "01" in the lower two bits, and an information intrinsic to a design can be incorporated into this pattern. The data of the instruction register 53 can be read out through the test data output TDO while shifting the data.
When the state is transferred to the SHIFT-IR state (S206), the shift registers forming the instruction register 53 are connected to the test data input TDI and the test data output TDO. When the test mode selecting signal TMS is "0", and every time the test clock signal TCK rises, the data are shifted toward the test data output TDO. If the instruction register 53 is constituted with 8 bits, repeating the shift operation eight times enables specific data to be written into the instruction register 53. Furthermore, sending out the data of the instruction register 53 to the test data output TDO while repeating the shift operation enables the data of the instruction register 53 to be read out.
When the shift operation finishes, the state is transferred to the EXIT1-IR state (S207) to end the scan operation. In this EXIT1-IR state (S207), setting the test mode selecting signal TMS to "0" and rising the test clock signal TCK transfers the state to the PAUSE-IR state (S208); setting the test mode selecting signal TMS to "1" and rising the test clock signal TCK transfers the state to the UPDATE-IR state (S210).
When the state is transferred to the PAUSE-IR state (S208), the shift operation of the instruction register 53 is paused in a serial pass between the test data input TDI and the test data output TDO. This state is utilized when a new pattern is loaded into an internal memory from an external memory.
In the PAUSE-IR state (S208), setting the test mode selecting signal TMS to "1" and rising the test clock signal TCK transfers the state to the EXIT2-IR state (S209) to stop the scan. When the scan operation is further needed, in the EXIT2-IR state (S209), setting the test mode selecting signal TMS to "0" and rising the test clock signal TCK transfers the state again to the SHIFT-IR state (S206) to perform the shift operation. when ending the scan operation, in the EXIT2-IR state (S209), setting the test mode selecting signal TMS to "1" transfers the state to the next UPDATE-IR state (S210).
When the state is transferred to the UPDATE-IR state (S210), new instruction data shifted to the shift registers are latched to be sent out in parallel When all the data are completely latched, execution of the instruction starts.
If a bypass instruction is loaded, for example, into the instruction register 53, the bypass register 522 is selected and is connected to the test data input TDI and the test data output TDO so as to bypass the data by the shift operation.
If an instruction "JIR SET" or "JDR SET" is loaded into the instruction register 53, the JIR 523 or JDR 524 is selected and is connected to the test data input TDI and the test data output TDO so as to execute the data loading into the JIR 523 or JDR 524 and the data sensing from the JIR 523 or JDR 524, namely, the data scanning by the sift operation.
On the other hand, the state S203 and S211 through S216 in FIG. 8 shows the state in which the scan operation is executed to the boundary scan register 521, bypass register 522, JIR 523, or JDR 524.
When comparing the scan operation by the state S203 and S211 through S216 with the scan operation to the instruction register 53 described in the state S204 through S210, there are differences in the two points: (a) the registers to be scanned are four registers 521 through 524 of the data register group 52 against the instruction register 53; (b) the number of shifting in the scan operation is varied depending on which one of the registers 521 through 524 is selected to be scanned.
However, the state transition is substantially the same, the state S203 and the S211 through S216 correspond to the state S204 through S210, respectively, and the description will be omitted.
In the denotation of the state S204 through S210, "IR" meaning the instruction register 53 is changed into "DR" meaning the data register 52 in the denotation of the state S203 and the S211 through S216, which is a difference in the notation.
FIG. 9 illustrates a total construction of a processing system (computer system) employing chip parts into which the JTAG circuit described above with FIGS. 7 and 8 is incorporated. The processing system is comprised of a service processor (hereunder, abbreviated as SVP) 101, an interface circuit hereunder, abbreviated as SCI(System Console Interface)! 102, and a mother board 103.
The SVP 101 is connected to the mother board 103 through the SCI 102 to control the maintenance and operation of the total system. The SVP 101 issues commands to control: the registers in the printed circuit boards 103-1 through 103-m constituting the mother board 103, a data-write into a memory, and a data read-out from a memory.
The chip parts such as LSIs mounted on the printed circuit boards 103-1 through 103-m are provided with the JTAG circuits described in FIG. 7. The SVP 101 also controls the JTAG circuits through the SCI 102. Accordingly, the SCI 102 and the printed circuit boards 103-1 through 103-m in the mother board 103 are connected by signal lines 104 to transmit and receive commands and data so as to control the JTAG circuits.
Incidentally, the conventional computer system has been trying to improve the performance of the central processing unit (CPU) itself in order to cope with users' needs. However, with this approach alone, the increasing users' needs cannot be satisfied in some aspects, and recently, the parallel processing computer has attracted a considerable attention.
The parallel processing computer constitutes one computer system in which several to some hundreds of processing units called processor element (PE) are connected to be able to communicate each other, and the PEs each can execute the processes, thereby improving performance as a system by executing the parallel processes.
The units constituting such a computer system each are composed of a plurality of printed circuit boards as shown in FIG. 9. The printed circuit boards each are provided with a clock signal from a clock oscillator, and a plurality of the printed circuit boards operate synchronously with the clock signal. However, the printed circuit boards each have intrinsic characteristics of their own, and generally, the circuit boards having an identical circuit construction will have deviations in the operational timing among the printed circuit boards.
In order to annul the deviations in the timing, clock tuning latches are provided on each of the printed circuit boards. Setting specific clock tuning data according to the characteristics of the printed circuit boards to the corresponding latches and making the clock timing to coincide with each other among the printed circuit boards will annul the deviation in the timing so that the total unit can operate synchronously with one clock.
The process to set specific clock tuning data to clock tuning latches is called a clock tuning process. Generally, this clock tuning process is done for a start-up period of the system from the moment the system is powered to the start of the operation, as follows.
In the units constituting the computer system, continuously connecting the clock tuning latches on the printed circuit boards forms one loop (tuning scan loop), and sending the clock tuning data to be set to the latches into the foregoing loop sequentially according to the sequence to connect the latches and repeating the shift loads the clock tuning data into the specific latch. The clock tuning data and the data intrinsic to the printed circuit boards which are necessary for the start-up of the system, and others are stored in advance in an EEPROM described later in FIG. 10 or the like, and are read out from the EEPROM or the like at the start-up.
Next, FIG. 10 illustrates a construction of important parts of the processing system that performs the foregoing clock tuning process. The processing system shown in FIG. 10 is virtually identical to the processing system shown in FIG. 9. FIG. 10 further illustrates a detailed construction of the printed circuit board 103-x functioning as an MCU (Main Control Unit) of a plurality of the printed circuit boards constituting the mother board 103 and a detailed construction of the SCI 102.
As shown in FIG. 10, the printed circuit board 103-x includes three LSI-1, LSI-2, and LSI-3, each of which is provided with the JTAG circuit as a JTAG testing unit 100 as described in FIG. 6 or 7. Connecting these JTAG testing units 100 in a chain forms a round scan chain in the printed circuit board 103-x. And, the SCI 102 is provided with a JTAG control unit 104 that controls the JTAG testing units 100 namely, writes desired data into the registers (refer to FIG. 7) of the JTAG testing units 100.
Furthermore, the system shown in FIG. 10 is provided with an EEPROM (nonvolatile memory) 105 of, for example, 8 Kbytes connected to the LSI-2 in the printed circuit board 103-x functioning as an MCU. This EEPROM 105 holds the clock tuning data of the printed circuit boards constituting the mother board 103, and the other data necessary for the start-up of the system that are intrinsic to the printed circuit boards.
At the start-up of the processing system, the data stored in the EEPROM 105 needed to be read out in order to execute the foregoing clock tuning process. Accordingly, the processing system shown in FIG. 10 is provided with, apart from the aforementioned JTAG testing units 100 and the JTAG control unit 104, a data load unit 106, EEPROM read-out control unit 107, and data transfer unit 108 on the SCI 102, and is provided with an address write unit 109 and address register (ADRS) 110 on the LSI-2 connected to the EEPROM 105.
The data load unit 106 receives data read-out designating data as well as address data (leading address, read-out data number) at the start-up of the processing system from the SVP 101, and sends the leading address of the data to be read out to the 20 address write unit 109 in the LSI-2 of the printed circuit board 103-x.
The address write unit 109 sets the leading address from the data load unit 106 to the address register 110, and the data in an address set in the address register 110 are read out from the EEPROM 105 to the EEPROM read-out control unit 107.
The EEPROM read-out control unit 107 sends out a count-up designation address-up (AD UP)signal! to the address register 110 in order to count up the address set to the address register 110 one by one for the read-out data number from the leading address, and on the other hand sends out the data read out from the EEPROM 105 to the data transfer unit 108. The data transfer unit 108 transfers the data read out from the EEPROM 105 to a memory (DM) 111 for a DMA (Direct Memory Access) of the SVP 101.
According to the foregoing construction at the start-up of the processing system, the read-out designation such as the clock tuning data as well as the address data (leading address, read-out data number) are sent out to the data load unit 106 of the SCI 102 from the SVP 101. The leading address of the address data is sent out from the data load unit 106 through the address write unit 109 to be set to the address register 110 in the LSI-2.
The data in accordance with the address set to the address register 110 are read out from the EEPROM 105, and the read-out data are transferred to the DM 111 of the SVP 101 through the EEPROM read-out control unit 107 and the data transfer unit 108. The address set to the address register 110 is counted up one by one for the read-out data number from the leading address by the EEPROM read-out control unit 107, and the data such as the clock tuning data requested by the SVP 101 are sequentially read out from the EEPROM 105 into the SVP 101. And, the SVP 101 executes the initialization of the clock tuning process and the like using the read out data.
However, the processing system shown in FIG. 10 has to be provided with a single-purpose circuit as a mechanism to read out the clock tuning data and the like stored in the EEPROM 105, namely, the data load unit 106, EEPROM read-out control unit 107, address write unit 109 and the like, which invites complexity of the circuit construction.